This invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
As is well known in the art, a semiconductor memory has cell transistors and peripheral transistors formed on the same substrate. As one example thereof, an electrically erasable and programmable read only memory in which data erasing and programming can be electrically effected is well known.
FIG. 1 shows an EEPROM. That is, FIG. 1 schematically shows the construction of cell transistors (including selection gate transistors) and peripheral transistors of a conventional NAND type EEPROM.
The construction of the cell transistor and peripheral transistor of the NAND type EEPROM is explained below according to the manufacturing process thereof.
FIGS. 2A to 2D show the manufacturing process of the cell transistors and peripheral transistors of the conventional NAND type EEPROM.
First, as shown in FIG. 2A, for example, after a well region and element isolation region (neither of them is shown in the drawing) are formed in the surface area of a silicon substrate 101, a thermal oxidation film 102 used as a gate insulating film or tunnel oxide film is formed on the well region.
Then, in the memory cell region, gate electrodes 103 of stacked gate structure are formed on the thermal oxidation film (tunnel oxide film) 102 and, in the peripheral circuit region, gate electrodes 104 of single-layered structure are formed on the thermal oxide film (gate insulating film) 102.
The gate electrode 103 in the memory cell region has a well known structure in which, for example, a control gate electrode 103c is stacked on a floating gate 103a used as a charge storing layer while an ONO film (oxide film/nitride film/oxide film) 103b used as an inter-gate insulating film is disposed therebetween.
Next, as shown in FIG. 2B, post-oxidation films 105 for restoring the gate electrodes 103, 104 from the processing damage are formed.
Then, as shown in FIG. 2C, impurity 106 is implanted to form source and drain diffusion regions of the respective transistors.
After this, as shown in FIG. 2D, the implanted impurity 106 is activated by annealing and driven towards the channel region side to form source and drain diffusion layers 106′.
Next, after an inter-level insulating film 107 is formed on the structure, contacts 108 and inter-connection layers 109 connected to the electrodes 104 and contacts 110 and bit lines 111 connected to the source/drain diffusion layers 106′ are formed to form the cell transistors and peripheral transistors of the structure shown in FIG. 1.
However, if the conventional cell transistors and peripheral transistors are formed as described above, the length of the overlap area of the source/drain diffusion layer 106′ over the gate electrode 103 or 104 varies depending on the condition of the annealing process effected after the impurity 106 is implanted.
For example, if the annealing process is not sufficiently effected and the source/drain diffusion layer 106′ does not overlap and is offset from the gate electrode 103 or 104, the offset portion acts as a parasitic resistor to prevent a sufficiently large drain current from flowing in the device.
On the other hand, if the annealing process is excessively effected and the source/drain diffusion layer 106′ extends deeply into the channel region, the short channel effect becomes significant and the source-drain withstand voltage is lowered, thereby degrading the device characteristic.
Generally, the gate length in the memory cell is shorter than that in the peripheral transistor. Therefore, the short channel effect in the memory cell tends to become more noticeable. That is, if the annealing process is sufficiently effected for the peripheral transistor, there occurs a possibility that punch through may occur in the cell transistor and selection transistor.
In the case of NAND type EEPROM, since the source and drain diffusion layers 106′ of the memory cells are satisfactory if they can electrically connect the cells which are serially arranged, it is not necessary to overlap the source/drain diffusion layer 106′ over the gate electrode 103. That is, it can be the that the annealing process after the impurity 106 is implanted is effected to the least possible degree from the viewpoint of the characteristic of the cell transistor and selection transistor.
Further, in the case of the post-oxidation amount after the gate processing, the post-oxidation for sufficiently compensating for the processing damage is necessary, but the post-oxidation increases the bird's beak amount. In a case where the memory cell has a short gate, an increase in the bird' beak amount by the post-oxidation (refer to a portion A in FIG. 1, for example) lowers the coupling ratio, degrades the programming and erasing characteristics and is not preferable.
In the case of the peripheral transistor, since the gate is relatively long, it is permitted to sufficiently effect the post-oxidation (refer to a portion B in FIG. 1, for example).
Thus, since the NAND type EEPROM includes transistors having different gate lengths and the post-oxidation amount and the most suitable annealing condition for impurity diffusion are different depending on the gate lengths of the transistors, the difference causes a main factor which lowers the process margin.